NUMBER NAME LEADING PARTNER DISSEMINATION LEVEL STATUS
D2.1 Collaboration method to define the use cases and requirements AVL-TR SENSIBLE APPROVED
D2.2 Use cases and requirements AVL-TR SENSIBLE SUBMITTED – PENDING APPROVAL
D2.3 Test Cases AVL-TR PUBLIC SUBMITTED – PENDING APPROVAL
D2.4 Gap analysis and change management report M24 AVL-TR SENSIBLE
D2.5 Gap analysis and change management report M36 AVL-TR SENSIBLE
D2.6 Gap analysis and change management report M44 AVL-TR SENSIBLE
D3.1 Selection of switching-cell main power semiconductor devices CSIC PUBLIC APPROVED
D3.2 Switching-cell functionality and schematic UPC SENSIBLE
D3.3 Configuration of the converter legs UPC SENSIBLE
D3.4 Definition of the baseline secondary control UPC SENSIBLE
D3.5 Selection of converter topologies UPC SENSIBLE
D3.6 Definition of the baseline tertiary control UPC SENSIBLE
D3.7 Guidelines for the design of modular and scalable EV powertrain architectures UPC PUBLIC
D4.1 Definition of the power chip-embedding manufacturing process flow and design rules CSIC SENSIBLE APPROVED
D4.2 Individual SC manufacturing based on power chip-embedding CSIC SENSIBLE
D4.3 Critical design rules review Deep Concept SENSIBLE
D4.4 Power converter legs manufacturing based on power chip-embedding Deep Concept SENSIBLE
D5.1 Ruggedness and aging analysis of selected power semiconductor devices CSIC PUBLIC SUBMITTED – PENDING APPROVAL
D5.2 Ruggedness and aging analysis of the SCs CSIC PUBLIC
D5.3 Designs of the OMSs for PHM and SoH purposes TEKNE PUBLIC
D5.4 Digital twin compact models IREC SENSIBLE
D5.5 Advanced modulations and control strategies and PHM algorithms for optimized performance, EMI reduction, PHM, and SoH enhancement UNIMORE SENSIBLE
D6.1 Inverter/OBC mock-up prototype IREC SENSIBLE
D6.2 Inverter/OBC final prototype AVL-DE SENSIBLE
D6.3 Auxiliary dc-dc converter final prototype IREC SENSIBLE
D6.4 Mechanical design plans & simulation results of the integration of the power electronics converters into an e-axle and a battery pack UNIMORE PUBLIC